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ECRTS
2006
IEEE
15 years 8 months ago
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
Isabelle Puaut
INFOCOM
2005
IEEE
15 years 8 months ago
A distributed adaptive cache update algorithm for the dynamic source routing protocol
On-demand routing protocols use route caches to make routing decisions. Due to frequent topology changes, cached routes easily become stale. To address the cache staleness issue i...
Xin Yu, Zvi M. Kedem
RTSS
1994
IEEE
15 years 6 months ago
Bounding Worst-Case Instruction Cache Performance
The use of caches poses a difficult tradeoff for architects of real-time systems. While caches provide significant performance advantages, they have also been viewed as inherently...
Robert D. Arnold, Frank Mueller, David B. Whalley,...
ISCA
2007
IEEE
143views Hardware» more  ISCA 2007»
15 years 8 months ago
Interconnect design considerations for large NUCA caches
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
Naveen Muralimanohar, Rajeev Balasubramonian
DAC
2007
ACM
16 years 3 months ago
A Self-Tuning Configurable Cache
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
Ann Gordon-Ross, Frank Vahid