In this paper, we propose a novel cache consistency maintenance scheme, called Ë Ð Ð ×ÝÒ ÖÓÒÓÙ× ÓÒ× ×Ø Ò Ý Ë Ñ (SACCS), for mobile environments. It relies on ...
In this paper, we propose a cache design that provides the same miss rate as a two-way set associative cache, but with a access time closer to a direct-mapped cache. As with other...
Trace-driven simulation of superscalar processors is particularly complicated. The dynamic nature of superscalar processors combined with the static nature of traces can lead to l...
In this paper, we reevaluate the use of adaptive compressed caching to improve system performance through the reduction of accesses to the backing stores. We propose a new adaptab...
Rodrigo S. de Castro, Alair Pereira do Lago, Dilma...
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...