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INFOCOM
2007
IEEE
14 years 2 months ago
On the Extreme Parallelism Inside Next-Generation Network Processors
Next-generation high-end Network Processors (NP) must address demands from both diversified applications and ever-increasing traffic pressure. One major challenge is to design an e...
Lei Shi, Yue Zhang 0006, Jianming Yu, Bo Xu, Bin L...
PVLDB
2010
166views more  PVLDB 2010»
13 years 6 months ago
Complex Event Detection at Wire Speed with FPGAs
Complex event detection is an advanced form of data stream processing where the stream(s) are scrutinized to identify given event patterns. The challenge for many complex event pr...
Louis Woods, Jens Teubner, Gustavo Alonso
HOTI
2005
IEEE
14 years 2 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu
HOTI
2005
IEEE
14 years 2 months ago
Addressing Queuing Bottlenecks at High Speeds
Modern routers and switch fabrics can have hundreds of input and output ports running at up to 10 Gb/s; 40 Gb/s systems are starting to appear. At these rates, the performance of ...
Sailesh Kumar, Jonathan S. Turner, Patrick Crowley
PVM
2004
Springer
14 years 1 months ago
Numerical Simulations on PC Graphics Hardware
On recent PC graphics cards, fully programmable parallel geometry and pixel units are available providing powerful instruction sets to perform arithmetic and logical operations. In...
Jens Krüger, Thomas Schiwietz, Peter Kipfer, ...