240 search results - page 45 / 48 » To be fair or efficient or a bit of both |
TMC
2008
13 years 7 months ago
2008
Recently wireless sensor networks featuring direct sink access have been studied as an efficient architecture to gather and process data for numerous applications. In this paper, w...
IPPS
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract-- Recent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The cache par...
SIGOPS
2010
13 years 2 months ago
2010
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
TON
2010
13 years 2 months ago
2010
Abstract--A framework for designing feedback-based scheduling algorithms is proposed for elegantly solving the notorious packet missequencing problem of a load-balanced switch. Unl...
ISLPED
2010
ACM
13 years 7 months ago
2010
ACM
Memories play a key role in FGPAs in the forms of both programming bits and embedded memory blocks. FPGAs using non-volatile memories have been the focus of attention with zero bo...