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DSD
2003
IEEE
138views Hardware» more  DSD 2003»
14 years 1 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
EDOC
2009
IEEE
14 years 2 months ago
Using Enterprise Architecture Management Patterns to Complement TOGAF
—The design of an Enterprise Architecture (EA) management function for an enterprise is no easy task. Various frameworks exist as well as EA management tools, which promise to de...
Sabine Buckl, Alexander M. Ernst, Florian Matthes,...
FPGA
2004
ACM
147views FPGA» more  FPGA 2004»
14 years 1 months ago
The SFRA: a corner-turn FPGA architecture
FPGAs normally operate at whatever clock rate is appropriate for the loaded configuration. When FPGAs are used as computational devices in a larger system, however, it is better ...
Nicholas Weaver, John R. Hauser, John Wawrzynek
LCN
2008
IEEE
14 years 2 months ago
DiCAP: Distributed Packet Capturing architecture for high-speed network links
— IP traffic measurements form the basis of several network management tasks, such as accounting, planning, intrusion detection, and charging. High-speed network links challenge ...
Cristian Morariu, Burkhard Stiller
EUROPAR
2003
Springer
14 years 1 months ago
Distributed Application Monitoring for Clustered SMP Architectures
Abstract. Performance analysis for terascale computing requires a combination of new concepts including distribution, on-line processing and automation. As a foundation for tools r...
Karl Fürlinger, Michael Gerndt