Sciweavers

35 search results - page 5 / 7
» Topologically constrained logic synthesis
Sort
View
ICN
2009
Springer
14 years 3 months ago
New Algorithm for the Design of Topology Aware Hypercube in Multi-hop Ad Hoc Networks
Securing group communications in resource constrained, infrastructure-less environments such as Mobile Ad Hoc Networks (MANETs) has become one of the most challenging research dire...
Maria Striki, Kyriakos Manousakis, John S. Baras
TCAD
2008
118views more  TCAD 2008»
13 years 10 months ago
CHIPS: Custom Hardware Instruction Processor Synthesis
This paper describes an integer-linear-programming (ILP)-based system called Custom Hardware Instruction Processor Synthesis (CHIPS) that identifies custom instructions for critica...
Kubilay Atasu, Can C. Özturan, Günhan D&...
CDES
2008
87views Hardware» more  CDES 2008»
14 years 10 days ago
Finding Minimal ESCT Expressions for Boolean Functions with Weight of up to 7
In this paper an algorithm is proposed for the synthesis and exact minimization of ESCT (Exclusive or Sum of Complex Terms) expressions for Boolean functions of up to seven comple...
Dimitrios Voudouris, Marinos Sampson, George K. Pa...
INTEGRATION
2008
89views more  INTEGRATION 2008»
13 years 11 months ago
Exact ESCT minimization for functions of up to six input variables
In this paper an efficient algorithm for the synthesis and exact minimization of ESCT(Exclusive or Sum of Complex Terms) expressions for Boolean functions of at most six variables...
Dimitrios Voudouris, Marinos Sampson, George K. Pa...
ECCTD
2011
72views more  ECCTD 2011»
12 years 10 months ago
Managing variability for ultimate energy efficiency
⎯ Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate th...
Borivoje Nikolic