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» Towards Nanoelectronics Processor Architectures
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CF
2005
ACM
13 years 9 months ago
Balancing clustering-induced stalls to improve performance in clustered processors
Clustered processors lose performance as a result of clusteringinduced stalls. Such stalls are the result of distributed resources and cluster communication delays. Our performanc...
Amirali Baniasadi
IPPS
2005
IEEE
14 years 1 months ago
Configuration Steering for a Reconfigurable Superscalar Processor
An architecture for a reconfigurable superscalar processor is described in which some of its execution units are implemented in reconfigurable hardware. The overall configuration ...
Brian F. Veale, John K. Antonio, Monte P. Tull
ISCA
2007
IEEE
114views Hardware» more  ISCA 2007»
14 years 1 months ago
Mechanisms for bounding vulnerabilities of processor structures
Concern for the increasing susceptibility of processor structures to transient errors has led to several recent research efforts that propose architectural techniques to enhance r...
Niranjan Soundararajan, Angshuman Parashar, Anand ...
DAC
2007
ACM
14 years 8 months ago
Chip Multi-Processor Generator
The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, ...
Alex Solomatnikov, Amin Firoozshahian, Wajahat Qad...
AAECC
2007
Springer
87views Algorithms» more  AAECC 2007»
13 years 7 months ago
Towards an accurate performance modeling of parallel sparse factorization
We present a simulation-based performance model to analyze a parallel sparse LU factorization algorithm on modern cached-based, high-end parallel architectures. We consider supern...
Laura Grigori, Xiaoye S. Li