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ISCA
2007
IEEE
114views Hardware» more  ISCA 2007»
14 years 4 months ago
Mechanisms for bounding vulnerabilities of processor structures
Concern for the increasing susceptibility of processor structures to transient errors has led to several recent research efforts that propose architectural techniques to enhance r...
Niranjan Soundararajan, Angshuman Parashar, Anand ...
FTRTFT
1998
Springer
14 years 2 months ago
Towards a Formal Semantics of Verilog Using Duration Calculus
Gerardo Schneider, Qiwen Xu