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MICRO
1996
IEEE
129views Hardware» more  MICRO 1996»
14 years 22 days ago
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...
Eric Rotenberg, Steve Bennett, James E. Smith
PEPM
2011
ACM
12 years 11 months ago
Allocation removal by partial evaluation in a tracing JIT
The performance of many dynamic language implementations suffers from high allocation rates and runtime type checks. This makes dynamic languages less applicable to purely algorit...
Carl Friedrich Bolz, Antonio Cuni, Maciej FijaBkow...
HICSS
1997
IEEE
90views Biometrics» more  HICSS 1997»
14 years 23 days ago
A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors
We describe an environment to produce traces representing significant workloads for a shared-bus shared-memory multiprocessor used as a general-purpose multitasking machine, wher...
Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Pr...
ARCS
2006
Springer
14 years 9 days ago
Do Trace Cache, Value Prediction and Prefetching Improve SMT Throughput?
While trace cache, value prediction, and prefetching have been shown to be effective in the single-threaded superscalar, there has been no analysis of these techniques in a Simulta...
Chen-Yong Cher, Il Park, T. N. Vijaykumar
TC
2002
13 years 8 months ago
On Augmenting Trace Cache for High-Bandwidth Value Prediction
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction and speculatively executes its data-dependent instructions based on th...
Sang Jeong Lee, Pen-Chung Yew