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SBACPAD
2003
IEEE
75views Hardware» more  SBACPAD 2003»
14 years 3 months ago
The Limits of Speculative Trace Reuse on Deeply Pipelined Processors
Trace reuse improves the performance of processors by skipping the execution of sequences of redundant instructions. However, many reusable traces do not have all of their inputs ...
Maurício L. Pilla, Amarildo T. da Costa, Fe...
SPAA
2003
ACM
14 years 3 months ago
Throughput-centric routing algorithm design
The increasing application space of interconnection networks now encompasses several applications, such as packet routing and I/O interconnect, where the throughput of a routing a...
Brian Towles, William J. Dally, Stephen P. Boyd
FOCS
2002
IEEE
14 years 2 months ago
Minimizing Congestion in General Networks
A principle task in parallel and distributed systems is to reduce the communication load in the interconnection network, as this is usually the major bottleneck for the performanc...
Harald Räcke
CAL
2006
13 years 10 months ago
A Case for Compressing Traces with BDDs
Instruction-level traces are widely used for program and hardware analysis. However, program traces for just a few seconds of execution are enormous, up to several terabytes in siz...
Graham D. Price, Manish Vachharajani
PVM
2010
Springer
13 years 8 months ago
Locality and Topology Aware Intra-node Communication among Multicore CPUs
A major trend in HPC is the escalation toward manycore, where systems are composed of shared memory nodes featuring numerous processing units. Unfortunately, with scale comes compl...
Teng Ma, George Bosilca, Aurelien Bouteiller, Jack...