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RTSS
1994
IEEE
15 years 10 months ago
Guaranteeing End-to-End Timing Constraints by Calibrating Intermediate Processes
This paper presents a comprehensive design methodology for guaranteeing end-to-end requirements of real-time systems. Applications are structured as a set of process components co...
Richard Gerber, Seongsoo Hong, Manas Saksena
ATAL
2007
Springer
15 years 10 months ago
Workflow coordination for service-oriented multiagent systems
From a multiagent viewpoint, a workflow is a dynamic set of tasks performed by a set of agents to reach a shared goal. We show herein that commitments among agents can be used to ...
Jiangbo Dang, Jingshan Huang, Michael N. Huhns
CF
2007
ACM
15 years 10 months ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
DAC
2009
ACM
15 years 10 months ago
NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core
Traditional debug methodologies are limited in their ability to provide debugging support for many-core parallel programming. Synchronization problems or bugs due to race conditio...
Chi-Neng Wen, Shu-Hsuan Chou, Tien-Fu Chen, Alan P...
ATS
2004
IEEE
87views Hardware» more  ATS 2004»
15 years 10 months ago
Low Power BIST with Smoother and Scan-Chain Reorder
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...
Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu