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» Transfer Function Based Approaches to Array Calibration
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TNN
2010
147views Management» more  TNN 2010»
13 years 2 months ago
Theoretical Model for Mesoscopic-Level Scale-Free Self-Organization of Functional Brain Networks
In this paper we provide theoretical and numerical analysis of a geometric activity flow network model which is aimed at explaining mathematically the scale-free functional graph s...
J. Piersa, Filip Piekniewski, Tomasz Schreiber
TVLSI
2008
133views more  TVLSI 2008»
13 years 7 months ago
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
Mitchell J. Myjak, José G. Delgado-Frias
DATE
2007
IEEE
106views Hardware» more  DATE 2007»
14 years 1 months ago
Design closure driven delay relaxation based on convex cost network flow
Design closure becomes hard to achieve at physical layout stage due to the emergence of long global interconnects. Consequently, interconnect planning needs to be integrated in hi...
Chuan Lin, Aiguo Xie, Hai Zhou
DATE
2005
IEEE
139views Hardware» more  DATE 2005»
14 years 1 months ago
EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation
This paper presents a new mathematical approach to modeling EM wave coupling noise so that it can be easily integrated into chip-level noise analysis tools. The new method employs...
Baohua Wang, Pinaki Mazumder
TVCG
2002
156views more  TVCG 2002»
13 years 7 months ago
A Hardware-Assisted Scalable Solution for Interactive Volume Rendering of Time-Varying Data
We present a scalable volume rendering technique that exploits lossy compression and low-cost commodity hardware to permit highly interactive exploration of time-varying scalar vol...
Eric B. Lum, Kwan-Liu Ma, John Clyne