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DSN
2007
IEEE
14 years 1 months ago
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
Christopher LaFrieda, Engin Ipek, José F. M...
DSN
2002
IEEE
14 years 13 days ago
Ditto Processor
Concentration of design effort for current single-chip Commercial-Off-The-Shelf (COTS) microprocessors has been directed towards performance. Reliability has not been the primary ...
Shih-Chang Lai, Shih-Lien Lu, Jih-Kwon Peir
USENIX
2007
13 years 9 months ago
A Memory Soft Error Measurement on Production Systems
Memory state can be corrupted by the impact of particles causing single-event upsets (SEUs). Understanding and dealing with these soft (or transient) errors is important for syste...
Xin Li, Kai Shen, Michael C. Huang, Lingkun Chu
NSDI
2008
13 years 9 months ago
BFT Protocols Under Fire
Much recent work on Byzantine state machine replication focuses on protocols with improved performance under benign conditions (LANs, homogeneous replicas, limited crash faults), ...
Atul Singh, Tathagata Das, Petros Maniatis, Peter ...
ENTCS
2007
113views more  ENTCS 2007»
13 years 7 months ago
Modular Checkpointing for Atomicity
Transient faults that arise in large-scale software systems can often be repaired by re-executing the code in which they occur. Ascribing a meaningful semantics for safe re-execut...
Lukasz Ziarek, Philip Schatz, Suresh Jagannathan