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» Transistor-Level Timing Analysis Using Embedded Simulation
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EMSOFT
2009
Springer
15 years 11 months ago
Cache-aware scheduling and analysis for multicores
The major obstacle to use multicores for real-time applications is that we may not predict and provide any guarantee on real-time properties of embedded software on such platforms...
Nan Guan, Martin Stigge, Wang Yi, Ge Yu
CASES
2006
ACM
15 years 10 months ago
Adaptive and flexible dictionary code compression for embedded applications
Dictionary code compression is a technique where long instructions in the memory are replaced with shorter code words used as index in a table to look up the original instructions...
Mats Brorsson, Mikael Collin
SAMOS
2010
Springer
15 years 2 months ago
A Polymorphic Register File for matrix operations
—Previous vector architectures divided the available register file space in a fixed number of registers of equal sizes and shapes. We propose a register file organization whic...
Catalin Bogdan Ciobanu, Georgi Kuzmanov, Georgi Ga...
RTSS
2003
IEEE
15 years 9 months ago
Experimental Evaluation of Code Properties for WCET Analysis
This paper presents a quantification of the timing effects that advanced processor features like data and instruction cache, pipelines, branch prediction units and out-oforder ex...
Antoine Colin, Stefan M. Petters
VISAPP
2007
15 years 5 months ago
Image deconvolution using a stochastic differential equation approach
We consider the problem of image deconvolution. We foccus on a Bayesian approach which consists of maximizing an energy obtained by a Markov Random Field modeling. MRFs are classi...
Xavier Descombes, M. Lebellego, Elena Zhizhina