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» Translating Software Designs for Model Checking
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CODES
2008
IEEE
13 years 9 months ago
Model checking SystemC designs using timed automata
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
Paula Herber, Joachim Fellmuth, Sabine Glesner
EWSA
2005
Springer
14 years 27 days ago
On the Systematic Conformance Check of Software Artefacts
Abstract. In this paper we present a systematic check of the conformance of the implemented and the intended software architecture. Nowadays industry is confronted with rapidly evo...
Hylke W. van Dijk, Bas Graaf, Rob Boerman
ICSE
2007
IEEE-ACM
14 years 7 months ago
Sequential Circuits for Relational Analysis
The Alloy tool-set has been gaining popularity as an alternative to traditional manual testing and checking for design correctness. Alloy uses a first-order relational logic for m...
Fadi A. Zaraket, Adnan Aziz, Sarfraz Khurshid
APSEC
2005
IEEE
14 years 1 months ago
A Formal Semantics of Timed Activity Diagrams and its PROMELA Translation
The lack of a precise semantics for UML activity diagrams makes the reasoning on models constructed using such diagrams infeasible. However, such diagrams are widely used in domai...
Nicolas Guelfi, Amel Mammar
FSEN
2009
Springer
13 years 11 months ago
Specification and Validation of Behavioural Protocols in the rCOS Modeler
The rCOS modeler implements the requirements modelling phase of a model driven component-based software engineering process. Components are specified in rCOS, a relational calculus...
Zhenbang Chen, Charles Morisset, Volker Stolz