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SAC
2010
ACM
13 years 6 months ago
A machine-checked soundness proof for an efficient verification condition generator
Verification conditions (VCs) are logical formulae whose validity implies the correctness of a program with respect to a specification. The technique of checking software properti...
Frédéric Vogels, Bart Jacobs 0002, F...
IFM
2010
Springer
152views Formal Methods» more  IFM 2010»
13 years 6 months ago
Specification and Verification of Model Transformations Using UML-RSDS
In this paper we describe techniques for the specification and verification of model transformations using a combination of UML and formal methods. The use of UML 2 notations to s...
Kevin Lano, Shekoufeh Kolahdouz Rahimi
ICFP
2005
ACM
14 years 9 months ago
Modular verification of concurrent assembly code with dynamic thread creation and termination
Proof-carrying code (PCC) is a general framework that can, in principle, verify safety properties of arbitrary machine-language programs. Existing PCC systems and typed assembly l...
Xinyu Feng, Zhong Shao
JSS
2010
120views more  JSS 2010»
13 years 3 months ago
Handling communications in process algebraic architectural description languages: Modeling, verification, and implementation
Architectural description languages are a useful tool for modeling complex systems at a high level of abstraction. If based on formal methods, they can also serve for enabling the...
Marco Bernardo, Edoardo Bontà, Alessandro A...
CCS
2007
ACM
14 years 3 months ago
Effect of static analysis tools on software security: preliminary investigation
Static analysis tools can handle large-scale software and find thousands of defects. But do they improve software security? We evaluate the effect of static analysis tool use on s...
Vadim Okun, William F. Guthrie, Romain Gaucher, Pa...