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» Two efficient methods to reduce power and testing time
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ICDE
2006
IEEE
162views Database» more  ICDE 2006»
16 years 5 months ago
Efficient Batch Top-k Search for Dictionary-based Entity Recognition
We consider the problem of speeding up Entity Recognition systems that exploit existing large databases of structured entities to improve extraction accuracy. These systems requir...
Amit Chandel, P. C. Nagesh, Sunita Sarawagi
BMCBI
2008
145views more  BMCBI 2008»
15 years 4 months ago
Mapping gene expression quantitative trait loci by singular value decomposition and independent component analysis
Background: The combination of gene expression profiling with linkage analysis has become a powerful paradigm for mapping gene expression quantitative trait loci (eQTL). To date, ...
Shameek Biswas, John D. Storey, Joshua M. Akey
ICNP
2003
IEEE
15 years 9 months ago
Packet Classification Using Extended TCAMs
CAMs are the most popular practical method for implementing packet classification in high performance routers. Their principal drawbacks are high power consumption and inefficient...
Ed Spitznagel, David E. Taylor, Jonathan S. Turner
INFORMATICALT
2000
123views more  INFORMATICALT 2000»
15 years 4 months ago
Cryptanalysis of the Batch Verifying Multiple RSA Digital Signatures
Recently, Harn proposed an efficient scheme that can batch verification multiple RSA digital signatures. His scheme can reduce signature verification time. However, there is a weak...
Min-Shiang Hwang, Iuon-Chang Lin, Kuo-Feng Hwang
RECOSOC
2007
118views Hardware» more  RECOSOC 2007»
15 years 5 months ago
A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems
Electronic equipments with higher performance, lower power consumption, and smaller size motivate the research for more efficient design methods. Platform-based design is a method...
Leandro Möller, Ismael Grehs, Ewerson Carvalh...