Sciweavers

4116 search results - page 129 / 824
» Type Analysis for CHIP
Sort
View
ISCAS
2006
IEEE
84views Hardware» more  ISCAS 2006»
14 years 2 months ago
Programmable synaptic weights for an aVLSI network of spiking neurons
—We describe a spiking neuronal network which allows local synaptic weights to be assigned to individual synapses. In previous implementations of neuronal networks, the biases th...
Yingxue Wang, Shih-Chii Liu
FPT
2005
IEEE
163views Hardware» more  FPT 2005»
14 years 2 months ago
Designing an FPGA SoC Using a Standardized IP Block Interface
Designing Systems on-Chip is becoming increasingly popular as die sizes increase and technology sizes decrease. The complexity of integrating different types of Processing Element...
Lesley Shannon, Blair Fort, Samir Parikh, Arun Pat...
IWSOC
2005
IEEE
151views Hardware» more  IWSOC 2005»
14 years 2 months ago
A Low Area and Low Power Programmable Baseband Processor Architecture
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
Eric Tell, Anders Nilsson, Dake Liu
ISLPED
2003
ACM
149views Hardware» more  ISLPED 2003»
14 years 2 months ago
Elements of low power design for integrated systems
The increasing prominence of portable systems and the need to limit power consumption and hence, heat dissipation in very high density VLSI chips have led to rapid and innovative ...
Sung-Mo Kang
AHS
2006
IEEE
145views Hardware» more  AHS 2006»
14 years 20 days ago
The Gannet Service-Based SoC: A Service-level Reconfigurable Architecture
We propose a novel type of dynamically reconfigurable System-on-Chip architecture, the Gannet service-based architecture. This novel concept addresses the issue of systemlevel rec...
Wim Vanderbauwhede