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TSMC
2008
137views more  TSMC 2008»
13 years 8 months ago
A Type-2 Self-Organizing Neural Fuzzy System and Its FPGA Implementation
This paper proposes a type-2 self-organizing neural fuzzy system (T2SONFS) and its hardware implementation. The antecedent parts in each T2SONFS fuzzy rule are interval type-2 fuzz...
Chia-Feng Juang, Yu-Wei Tsao
RTSS
2006
IEEE
14 years 2 months ago
Run-Time Services for Hybrid CPU/FPGA Systems on Chip
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...
Jason Agron, Wesley Peck, Erik Anderson, David L. ...
BMCBI
2004
131views more  BMCBI 2004»
13 years 8 months ago
Alternative mapping of probes to genes for Affymetrix chips
Background: Short oligonucleotide arrays have several probes measuring the expression level of each target transcript. Therefore the selection of probes is a key component for the...
Laurent Gautier, Morten Møller, Lennart Fri...
BMCBI
2010
91views more  BMCBI 2010»
13 years 7 months ago
Washing scaling of GeneChip microarray expression
Background: Post-hybridization washing is an essential part of microarray experiments. Both the quality of the experimental washing protocol and adequate consideration of washing ...
Hans Binder, Knut Krohn, Conrad J. Burden
PPOPP
2010
ACM
14 years 6 months ago
Does cache sharing on modern CMP matter to the performance of contemporary multithreaded programs?
Most modern Chip Multiprocessors (CMP) feature shared cache on chip. For multithreaded applications, the sharing reduces communication latency among co-running threads, but also r...
Eddy Z. Zhang, Xipeng Shen, Yunlian Jiang