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131
Voted
DFT
2006
IEEE
130views VLSI» more  DFT 2006»
15 years 8 months ago
Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream
Control flow checking (CFC) is a well known concurrent checking technique for ensuring that a program’s instruction execution sequence follows permissible paths. Almost all CFC...
Federico Rota, Shantanu Dutt, Sahithi Krishna
156
Voted
DSN
2011
IEEE
14 years 2 months ago
Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
Shuchang Shan, Yu Hu, Xiaowei Li
141
Voted
SAC
2004
ACM
15 years 8 months ago
GD-GhOST: a goal-oriented self-tuning caching algorithm
A popular solution to internet performance problems is the widespread caching of data. Many caching algorithms have been proposed in the literature, most attempting to optimize fo...
Ganesh Santhanakrishnan, Ahmed Amer, Panos K. Chry...
132
Voted
HPCA
1997
IEEE
15 years 6 months ago
Global Address Space, Non-Uniform Bandwidth: A Memory System Performance Characterization of Parallel Systems
Many parallel systems offer a simple view of memory: all storage cells are addresseduniformly. Despite a uniform view of the memory, the machines differsignificantly in theirmemo...
Thomas Stricker, Thomas R. Gross
104
Voted
ICDCSW
2003
IEEE
15 years 8 months ago
A Study of the Performance and Parameter Sensitivity of Adaptive Distributed Caching
A self-organized approach to manage a distributed proxy system called Adaptive Distributed Caching (ADC) has been proposed previously. We model each proxy as an autonomous agent th...
Markus J. Kaiser, Kwok Ching Tsui, Jiming Liu