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HICSS
1995
IEEE
109views Biometrics» more  HICSS 1995»
14 years 1 months ago
The architecture of an optimistic CPU: the WarpEngine
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
John G. Cleary, Murray Pearson, Husam Kinawi
CF
2005
ACM
14 years 21 hour ago
Sparse matrix storage revisited
In this paper, we consider alternate ways of storing a sparse matrix and their effect on computational speed. They involve keeping both the indices and the non-zero elements in t...
Malik Silva
SNPD
2003
13 years 11 months ago
Incomplete Information Processing for Optimization of Distributed Applications
This paper focuses on non-strict processing, optimization, and partial evaluation of MPI programs which use incremental data structures (ISs). We describe the design and implement...
Alfredo Cristóbal-Salas, Andrei Tchernykh, ...
SODA
1994
ACM
88views Algorithms» more  SODA 1994»
13 years 11 months ago
Optimal Prediction for Prefetching in the Worst Case
Response time delays caused by I/O are a major problem in many systems and database applications. Prefetching and cache replacement methods are attracting renewed attention because...
P. Krishnan, Jeffrey Scott Vitter
IJDE
2006
101views more  IJDE 2006»
13 years 10 months ago
Google Desktop as a Source of Digital Evidence
This paper discusses the emerging trend of Personal Desktop Searching utilities on desktop computers, and how the information cached and stored with these systems can be retrieved...
Benjamin Turnbull, Barry Blundell, Jill Slay