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ESTIMEDIA
2008
Springer
13 years 12 months ago
A framework for memory-aware multimedia application mapping on chip-multiprocessors
The relentless increase in multimedia embedded system application requirements as well as improvements in IC design technology have motivated the deployment of chip multiprocessor ...
Luis Angel D. Bathen, Nikil D. Dutt, Sudeep Pasric...
TPDS
2002
105views more  TPDS 2002»
13 years 9 months ago
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
Phil May, Santithorn Bunchua, D. Scott Wills
ICPP
2009
IEEE
13 years 7 months ago
Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs
This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this c...
Matteo Monchiero, Ramon Canal, Antonio Gonzá...
CODES
2011
IEEE
12 years 10 months ago
Memory controllers for high-performance and real-time MPSoCs: requirements, architectures, and future trends
Designing memory controllers for complex real-time and highperformance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must b...
Benny Akesson, Po-Chun Huang, Fabien Clermidy, Den...
ICDE
2005
IEEE
158views Database» more  ICDE 2005»
14 years 3 months ago
An Analysis of Spatio-Temporal Query Processing in Sensor Networks
Sensor networks are an emerging technology that provide new means to monitor and understand various phenomena. Nodes in a sensor network typically have a limited power supply, thu...
Alexandru Coman, Jörg Sander, Mario A. Nascim...