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CORR
2002
Springer
98views Education» more  CORR 2002»
15 years 4 months ago
Efficient Tree Layout in a Multilevel Memory Hierarchy
Stephen Alstrup, Michael A. Bender, Erik D. Demain...
MICRO
2010
IEEE
333views Hardware» more  MICRO 2010»
15 years 2 months ago
Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor
Pat Conway, Nathan Kalyanasundharam, Gregg Donley,...
ISCA
2007
IEEE
146views Hardware» more  ISCA 2007»
15 years 10 months ago
Virtual hierarchies to support server consolidation
Server consolidation is becoming an increasingly popular technique to manage and utilize systems. This paper develops CMP memory systems for server consolidation where most sharin...
Michael R. Marty, Mark D. Hill
EUROPAR
2009
Springer
15 years 8 months ago
Last Bank: Dealing with Address Reuse in Non-Uniform Cache Architecture for CMPs
In response to the constant increase in wire delays, Non-Uniform Cache Architecture (NUCA) has been introduced as an effective memory model for dealing with growing memory latenci...
Javier Lira, Carlos Molina, Antonio Gonzále...
ISCAS
2005
IEEE
97views Hardware» more  ISCAS 2005»
15 years 9 months ago
Two-level decoupled Hamming network for associative memory under noisy environment
— Compared with a single level Hamming associative memory, a simple model based on uniform random noise analysis has proved a twolevel decoupled Hamming network to be an efficie...
Liang Chen, Naoyuki Tokuda, Akira Nagai