This paper shows that, in an environment where we do not bound the number of faulty processes, the class P of Perfect failure detectors is the weakest (among realistic failure det...
In this paper we present an exhaustive evaluation of the memory subsystem in a chip-multiprocessor (CMP) architecture composed of 16 cores. The characterization is performed making...
This paper investigates the design of parallel algorithmic strategies that address the efficient use of both, memory hierarchies within each processor and a multilevel clustered ...
Frank K. H. A. Dehne, Stefano Mardegan, Andrea Pie...
We investigate the feasibility of using instruction compression at some level in a multi-level memory hierarchy to increase memory system performance. Compression e ectively incre...
A system that saves a digital copy of every document that users copy, print, or fax, without asking the user, has recently been proposed. Referred to as the Infinite Memory Multif...
Jonathan J. Hull, Dar-Shyang Lee, John F. Cullen, ...