Sciweavers

122 search results - page 23 / 25
» User-controllable coherence for high performance shared memo...
Sort
View
JPDC
2006
111views more  JPDC 2006»
13 years 6 months ago
Designing irregular parallel algorithms with mutual exclusion and lock-free protocols
Irregular parallel algorithms pose a significant challenge for achieving high performance because of the difficulty predicting memory access patterns or execution paths. Within an...
Guojing Cong, David A. Bader
HIPC
2005
Springer
14 years 3 days ago
Preemption Adaptivity in Time-Published Queue-Based Spin Locks
Abstract. The proliferation of multiprocessor servers and multithreaded applications has increased the demand for high-performance synchronization. Traditional scheduler-based lock...
Bijun He, William N. Scherer III, Michael L. Scott
MICRO
2010
IEEE
189views Hardware» more  MICRO 2010»
13 years 4 months ago
A Dynamically Adaptable Hardware Transactional Memory
Most Hardware Transactional Memory (HTM) implementations choose fixed version and conflict management policies at design time. While eager HTM systems store transactional state in-...
Marc Lupon, Grigorios Magklis, Antonio Gonzá...
POPL
2009
ACM
14 years 1 months ago
Low-pain, high-gain multicore programming in Haskell: coordinating irregular symbolic computations on multicore architectures
With the emergence of commodity multicore architectures, exploiting tightly-coupled parallelism has become increasingly important. Functional programming languages, such as Haskel...
Abdallah Al Zain, Kevin Hammond, Jost Berthold, Ph...
APPINF
2003
13 years 8 months ago
A Multithreaded Compiler Backend for High-level Array Programming
Whenever large homogeneous data structures need to be processed in a non-trivial way, e.g. in computational sciences, image processing, or system simulation, high-level array prog...
Clemens Grelck