501 search results - page 10 / 101 » Using Abstraction to Verify Arbitrary Temporal Properties |
ICCD
1995
IEEE
13 years 11 months ago
1995
IEEE
Symbolic model checking is a successful technique for checking properties of large finite-state systems. This method has been used to verify a number of real-world hardware desig...
FORMATS
2004
Springer
14 years 24 days ago
2004
Springer
Abstract. In this paper we introduce a variant of temporal logic tailored for specifying desired properties of continuous signals. The logic is based on a bounded subset of the rea...
ASYNC
2005
IEEE
14 years 1 months ago
2005
IEEE
We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not ...
CSSE
2008
IEEE
14 years 1 months ago
2008
IEEE
Abstract: The need of communication protocols in today’s environment increases as much as the network explores. Many new kinds of protocols, e.g. for information sharing, securit...
SIGSOFT
2007
ACM
14 years 8 months ago
2007
ACM
Model checking techniques have traditionally dealt with temporal logic languages and automata interpreted over -words, i.e., infinite in the future but finite in the past. However...