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SIGOPS
2010
179views more  SIGOPS 2010»
13 years 2 months ago
Online cache modeling for commodity multicore processors
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
Richard West, Puneet Zaroo, Carl A. Waldspurger, X...
ATAL
2005
Springer
14 years 26 days ago
Multi-agent decision support via user-modeling
Decision-support requires the gathering and presentation of information, but is subject to many kinds of resource restrictions (e.g. cost, length, time). Individual users differ n...
Terrence Harvey, Keith S. Decker, Sandra Carberry
HPCA
2011
IEEE
12 years 11 months ago
ACCESS: Smart scheduling for asymmetric cache CMPs
In current Chip-multiprocessors (CMPs), a significant portion of the die is consumed by the last-level cache. Until recently, the balance of cache and core space has been primari...
Xiaowei Jiang, Asit K. Mishra, Li Zhao, Ravishanka...
LCN
2005
IEEE
14 years 27 days ago
Implementation and Performance Analysis of a Packet Scheduler on a Programmable Network Processor
— The problem of achieving fairness in the allocation of the bandwidth resource on a link shared by multiple flows of traffic has been extensively researched over the last deca...
Fariza Sabrina, Salil S. Kanhere, Sanjay Jha
MSS
1999
IEEE
150views Hardware» more  MSS 1999»
13 years 11 months ago
Performance Benchmark Results for Automated Tape Library High Retrieval Rate Applications - Digital Check Image Retrievals
Benchmark tests have been designed and conducted for the purpose of evaluating the use of automated tape libraries in on-line digital check image retrieval applications. This type...
John Gniewek, George Davidson, Bowen Caldwell