16 search results - page 1 / 4 » Using Reference Counters in Update-Based Coherent Memory |
PARLE
1994
13 years 11 months ago
1994
Abstract. As the disparity between processor and memory speed continues to widen, the exploitation of locality of reference in shared-memory multiprocessors becomes an increasingly...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
High-performance multiprocessor systems built around out-of-order processors with aggressive branch predictors execute many memory references that turn out to be on a mispredicted...
ISCA
1998
IEEE
13 years 11 months ago
1998
IEEE
Most large shared-memory multiprocessors use directory protocols to keep per-processor caches coherent. Some memory references in such systems, however, suffer long latencies for ...
IEEEPACT
2005
IEEE
14 years 21 days ago
2005
IEEE
Coherence misses in shared-memory multiprocessors account for a substantial fraction of execution time in many important scientific and commercial workloads. Memory streaming prov...
ISCA
2011
IEEE
2011
IEEE
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks
12 years 10 months ago
To meet the demand for more powerful high-performance shared-memory servers, multiprocessor systems must incorporate efficient and scalable cache coherence protocols, such as thos...