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» Using Reference Counters in Update-Based Coherent Memory
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MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
13 years 5 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...
JPDC
2010
106views more  JPDC 2010»
13 years 5 months ago
Feedback-directed page placement for ccNUMA via hardware-generated memory traces
Non-uniform memory architectures with cache coherence (ccNUMA) are becoming increasingly common, not just for large-scale high performance platforms but also in the context of mul...
Jaydeep Marathe, Vivek Thakkar, Frank Mueller
ESANN
2007
13 years 8 months ago
Synchronization and acceleration: complementary mechanisms of temporal coding
Temporal coding is studied with an oscillatory network model that is a complex-valued generalization of the Cohen-Grossberg-Hopfield system. The model is considered with synchroni...
Thomas Burwick
IISWC
2009
IEEE
14 years 1 months ago
Understanding PARSEC performance on contemporary CMPs
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
Major Bhadauria, Vincent M. Weaver, Sally A. McKee
SIGGRAPH
1997
ACM
13 years 11 months ago
Rendering complex scenes with memory-coherent ray tracing
Simulating realistic lighting and rendering complex scenes are usually considered separate problems with incompatible solutions. Accurate lighting calculations are typically perfo...
Matt Pharr, Craig E. Kolb, Reid Gershbein, Pat Han...