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JSA
2010
158views more  JSA 2010»
14 years 9 months ago
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Je...
JSA
2010
173views more  JSA 2010»
14 years 9 months ago
Hardware/software support for adaptive work-stealing in on-chip multiprocessor
During the past few years, embedded digital systems have been requested to provide a huge amount of processing power and functionality. A very likely foreseeable step to pursue th...
Quentin L. Meunier, Frédéric P&eacut...
JSS
2010
120views more  JSS 2010»
14 years 9 months ago
Handling communications in process algebraic architectural description languages: Modeling, verification, and implementation
Architectural description languages are a useful tool for modeling complex systems at a high level of abstraction. If based on formal methods, they can also serve for enabling the...
Marco Bernardo, Edoardo Bontà, Alessandro A...
JUCS
2010
215views more  JUCS 2010»
14 years 9 months ago
A Multidisciplinary Survey of Computational Techniques for the Modelling, Simulation and Analysis of Biochemical Networks
: All processes of life are controlled by networks of interacting biochemical components. The purpose of modelling these networks is manifold. From a theoretical point of view it a...
James Decraene, Thomas Hinze
MACOM
2010
14 years 9 months ago
On the Performance of Single LDGM Codes for Iterative Data Fusion over the Multiple Access Channel
One of the applications of wireless sensor networks currently undergoing active research focuses on the scenario where the information generated by a data source S is simultaneousl...
Javier Del Ser, Javier Garcia-Frias, Pedro M. Cres...
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