8 search results - page 1 / 2 » Utilization of Cache Area in On-Chip Multiprocessor |
ISHPC
1999
Springer
14 years 3 months ago
1999
Springer
On-chip multiprocessor can be an alternative to the wide-issue superscalar processor approach which is currently the mainstream to exploit the increasing number of transistors on ...
ISCA
1998
IEEE
14 years 3 months ago
1998
IEEE
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a si...
MICRO
2007
IEEE
14 years 5 months ago
2007
IEEE
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
ICMCS
2005
IEEE
14 years 4 months ago
2005
IEEE
This paper studied an H.264 HDTV decoder on two multiprocessor system-on-chip architectures. Two types of networks-on-chip, the RAW network and the applicationspecific networks-on...
ISCA
2008
IEEE
14 years 5 months ago
2008
IEEE
Future chip multiprocessors (CMPs) may have hundreds to thousands of threads competing to access shared resources, and will require quality-of-service (QoS) support to improve sys...