46 search results - page 3 / 10 » VERILAT: verification using logic augmentation and transform... |
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
: A new approach to optimize multi-level logic circuits is introduced. Given a multi-level circuit, the synthesis method optimizes its area, simultaneously enhancing its random pat...
CORR
2009
Springer
13 years 5 months ago
2009
Springer
Abstract. We apply Uppaal Tiga to automatically compute adaptive scheduling strategies for an industrial case study dealing with a state-of-the-art image processing pipeline of a p...
40
Voted
ESWS
2009
Springer
13 years 5 months ago
2009
Springer
Abstract. In this paper we investigate the transformation of OWL-S process models to ISPL - the system description language for MCMAS, a symbolic model checker for multi agent syst...
POPL
2004
ACM
14 years 7 months ago
2004
ACM
We show how some classical static analyses for imperative programs, and the optimizing transformations which they enable, may be expressed and proved correct using elementary logi...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
We present an efficient search strategy for satisfiability checking on circuits represented at the register-transfer-level (RTL). We use the RTL circuit structure by extending con...