This paper describes an approach for VHDL-based communication and synchronization synthesis. This design step transforms a system level VHDL description into an RT-level descripti...
Abstract In this paper, we describe an automatic synthesis procedure that distributes synchronous programs on a set of desynchronized processing elements. Our distribution procedur...
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous design, this requires the consideration o...
Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhi...
This paper presents a novel IP core reuse strategy which reduces design time from days to hours for communication circuits such as digital radio receivers. This design productivity...
Adam Arnesen, Kevin Ellsworth, Derrick Gibelyou, T...
Complex system specifications are often hierarchically composed of several subsystems. Each subsystem contains one or more processes. In order to provide optimization across diffe...
Oliver Bringmann, Wolfgang Rosenstiel, Dirk Reicha...