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» Validating High-Level Synthesis
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FAC
2008
97views more  FAC 2008»
13 years 11 months ago
A functional formalization of on chip communications
This paper presents a formal model and a systematic approach to the validation of communication tures at a high level of abstraction. This model is described mathematically by a fu...
Julien Schmaltz, Dominique Borrione
SIGOPS
2010
105views more  SIGOPS 2010»
13 years 5 months ago
SelfTalk for Dena: query language and runtime support for evaluating system behavior
We introduce SelfTalk, a novel declarative language that allows users to query and understand the status of a large scale system. SelfTalk is sufficiently expressive to encode an ...
Saeed Ghanbari, Gokul Soundararajan, Cristiana Amz...
IJVR
2006
199views more  IJVR 2006»
13 years 11 months ago
Interactive Virtual Humans in Real-Time Virtual Environments
In this paper, we will present an overview of existing research in the vast area of IVH systems. We will also present our ongoing work on improving the expressive capabilities of I...
Nadia Magnenat-Thalmann, Arjan Egges
FCCM
2011
IEEE
220views VLSI» more  FCCM 2011»
13 years 2 months ago
Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems
— This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide ...
Manish Arora, Jack Sampson, Nathan Goulding-Hotta,...
COMPSAC
2000
IEEE
14 years 3 months ago
Automating Scenario-Driven Structured Requirements Engineering
Scenario analysis is a vehicle of separating concerns in the elicitation of users' requirements. It is also a means of requirements validation and verification. In the practi...
Hong Zhu, Lingzi Jin