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SRDS
2007
IEEE
14 years 1 months ago
The Fail-Heterogeneous Architectural Model
Fault tolerant distributed protocols typically utilize a homogeneous fault model, either fail-crash or fail-Byzantine, where all processors are assumed to fail in the same manner....
Marco Serafini, Neeraj Suri
ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
13 years 11 months ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani
DSN
2002
IEEE
14 years 13 days ago
Model Checking Safety Properties of Servo-Loop Control Systems
This paper presents the experiences of using a symbolic model checker to check the safety properties of a servoloop control system. Symbolic model checking has been shown to be be...
M. Edwin Johnson
DSD
2004
IEEE
136views Hardware» more  DSD 2004»
13 years 11 months ago
FPGA Based Design of the Railway's Interlocking Equipments
This paper describes the architecture of a safety system of the railway's interlocking equipment, which has been developed for Czech railways. The system will be used for the...
Radek Dobias, Hana Kubatova
MODELS
2009
Springer
14 years 2 months ago
Evaluating Context Descriptions and Property Definition Patterns for Software Formal Validation
A well known challenge in the formal methods domain is to improve their integration with practical engineering methods. In the context of embedded systems, model checking requires ...
Philippe Dhaussy, Pierre Yves Pillain, Stephen Cre...