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IPPS
2008
IEEE
14 years 4 months ago
Design of steering vectors for dynamically reconfigurable architectures
An architectural framework is studied that can perform dynamic reconfiguration. A basic objective is to dynamically reconfigure the architecture so that its configuration is well ...
Nick A. Mould, Brian F. Veale, John K. Antonio, Mo...
ISVLSI
2007
IEEE
181views VLSI» more  ISVLSI 2007»
14 years 3 months ago
Code-coverage Based Test Vector Generation for SystemC Designs
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...
Alair Dias Jr., Diógenes Cecilio da Silva J...
VR
2007
IEEE
195views Virtual Reality» more  VR 2007»
14 years 3 months ago
Active Text Drawing Styles for Outdoor Augmented Reality: A User-Based Study and Design Implications
A challenge in presenting augmenting information in outdoor augmented reality (AR) settings lies in the broad range of uncontrollable environmental conditions that may be present,...
Joseph L. Gabbard, J. Edward Swan II, Deborah Hix,...
TGC
2007
Springer
14 years 3 months ago
Service Oriented Architectural Design
Abstract. We propose Architectural Design Rewriting (ADR), an approach to formalise the development and reconfiguration of software architectures based on term-rewriting. An archi...
Roberto Bruni, Alberto Lluch-Lafuente, Ugo Montana...
IPPS
2006
IEEE
14 years 3 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...