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CLEIEJ
2010
13 years 6 months ago
3D-Via Driven Partitioning for 3D VLSI Integrated Circuits
A 3D circuit is the stacking of regular 2D circuits. The advances on the fabrication and packaging technologies allowed interconnecting stacked 2D circuits by using 3D vias. Howeve...
Sandro Sawicki, Gustavo Wilke, Marcelo O. Johann, ...
CVPR
2009
IEEE
15 years 4 months ago
A Multi-View Probabilistic Model for 3D Object Classes
We propose a novel probabilistic framework for learning visual models of 3D object categories by combining appearance information and geometric constraints. Objects are represen...
Fei-Fei Li 0002, Hao Su, Min Sun, Silvio Savarese
ICIP
2004
IEEE
14 years 10 months ago
Shape estimation of 3-D DNA molecules from stereo cryo-electron micro-graphs
We introduce a 3-D parametric active contour algorithm for the shape estimation of DNA molecules from stereo cryo-electron micrographs. We consider a 3-D filament (consisting of a...
Mathews Jacob, Thierry Blu, Michael Unser
ICPR
2006
IEEE
14 years 10 months ago
Chaining Planar Homographies for Fast and Reliable 3D Plane Tracking
This paper addresses the problem of tracking a 3D plane over a sequence of images acquired by a free moving camera, a task that is of central importance to a wide variety of visio...
Manolis I. A. Lourakis, Antonis A. Argyros
DAC
2007
ACM
14 years 10 months ago
Placement of 3D ICs with Thermal and Interlayer Via Considerations
Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during g...
Brent Goplen, Sachin S. Sapatnekar