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» Verification of Concurrent Programs with Chalice
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EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
13 years 12 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
ENTCS
2006
138views more  ENTCS 2006»
13 years 7 months ago
Variables as Resource in Separation Logic
Separation logic [20,21,14] began life as an extended formalisation of Burstall's treatment of list-mutating programs [8]. It rapidly became clear that there was more that it...
Richard Bornat, Cristiano Calcagno, Hongseok Yang
ENTCS
2006
97views more  ENTCS 2006»
13 years 7 months ago
VyrdMC: Driving Runtime Refinement Checking with Model Checkers
This paper presents VyrdMC, a runtime verification tool we are building for concurrent software components. The correctness criterion checked by VyrdMC is refinement: Each executi...
Tayfun Elmas, Serdar Tasiran