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» Verification of Equivalent-Results Methods
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IFIP
2001
Springer
14 years 2 months ago
Functional Test Generation using Constraint Logic Programming
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre
SRDS
1999
IEEE
14 years 2 months ago
Formal Hazard Analysis of Hybrid Systems in cTLA
Hybrid systems like computer-controlled chemical plants are typical safety critical distributed systems. In present practice, the safety of hybrid systems is guaranteed by hazard ...
Peter Herrmann, Heiko Krumm
NGITS
1999
Springer
14 years 2 months ago
From Object-Process Diagrams to a Natural Object-Process Language
As the requirements for system analysis and design become more complex, the need for a natural, yet formal way of specifying system analysis findings and design decisions are becom...
Mor Peleg, Dov Dori
EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
14 years 1 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
AOSD
2009
ACM
14 years 1 months ago
The dataflow pointcut: a formal and practical framework
Some security concerns are sensitive to flow of information in a program execution. The dataflow pointcut has been proposed by Masuhara and Kawauchi in order to easily implement s...
Dima Alhadidi, Amine Boukhtouta, Nadia Belblidia, ...