Sciweavers

1219 search results - page 69 / 244
» Verification of Equivalent-Results Methods
Sort
View
FMCAD
2004
Springer
14 years 1 months ago
Verification of Analog and Mixed-Signal Circuits Using Hybrid System Techniques
In this paper we demonstrate a potential extension of formal verification methodology in order to deal with time-domain properties of analog and mixed-signal circuits whose dynamic...
Thao Dang, Alexandre Donzé, Oded Maler
FORMATS
2006
Springer
14 years 1 months ago
Temporal Logic Verification Using Simulation
In this paper, we consider a novel approach to the temporal logic verification problem of continuous dynamical systems. Our methodology has the distinctive feature that enables the...
Georgios E. Fainekos, Antoine Girard, George J. Pa...
FTCS
1998
114views more  FTCS 1998»
13 years 11 months ago
Verification of a Safety-Critical Railway Interlocking System with Real-Time Constraints
Ensuring the correctness of computer systems used in lifecritical applications is very difficult. The most commonly used verification methods, simulation and testing, are not exha...
Vicky Hartonas-Garmhausen, Sérgio Vale Agui...
FMICS
2010
Springer
13 years 11 months ago
SMT-Based Formal Verification of a TTEthernet Synchronization Function
Abstract. TTEthernet is a communication infrastructure for mixedcriticality systems that integrates dataflow from applications with different criticality levels on a single network...
Wilfried Steiner, Bruno Dutertre
CSDA
2006
90views more  CSDA 2006»
13 years 10 months ago
Comparing two binary diagnostic tests in the presence of verification bias
The comparison of the accuracy of two binary diagnostic tests has traditionally required knowledge of the real state of the disease in all of the patients in the sample via the ap...
José Antonio Roldán Nofuentes, Juan ...