1219 search results - page 92 / 244 » Verification of Equivalent-Results Methods |
VLSI
2007
Springer
14 years 4 months ago
2007
Springer
— Software simulation remains the most used method for VHDL RTL functional verification. The functional verification process essentially consists of two parts. The first one is t...
IUI
2006
ACM
14 years 4 months ago
2006
ACM
Spoken dialog tasks incur many errors including speech recognition errors, understanding errors, and even dialog management errors. These errors create a big gap between user'...
IPPS
1999
IEEE
14 years 2 months ago
1999
IEEE
Abstract. We describe how the PVS verification system has been used to verify a safety property of a garbage collection algorithm, originally suggested by Ben-Ari. The safety prope...
FPL
2000
Springer
14 years 1 months ago
2000
Springer
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
CAV
2008
Springer
14 years 21 hour ago
2008
Springer
Program verification for relaxed memory models is hard. The high degree of nondeterminism in such models challenges standard verification techniques. This paper proposes a new veri...