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ISVLSI
2003
IEEE
157views VLSI» more  ISVLSI 2003»
15 years 9 months ago
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...
Shalini Ghosh, Sugato Basu, Nur A. Touba
ICALT
2010
IEEE
15 years 5 months ago
Improve the Output from a MCQ Test Item Generator Using Statistical NLP
In this study I use statistical Natural Language Processing and adapted Controlled Language methods to preprocess individual documents before they are used as source documents for ...
Robert Michael Foster
BMCBI
2006
147views more  BMCBI 2006»
15 years 4 months ago
A case study in pathway knowledgebase verification
Background: Biological databases and pathway knowledgebases are proliferating rapidly. We are developing software tools for computer-aided hypothesis design and evaluation, and we...
Stephen A. Racunas, Nigam Shah, Nina V. Fedoroff
SIGSOFT
2007
ACM
16 years 5 months ago
Quantitative verification: models techniques and tools
Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...
Marta Z. Kwiatkowska
PPOPP
2009
ACM
16 years 5 months ago
Formal verification of practical MPI programs
This paper considers the problem of formal verification of MPI programs operating under a fixed test harness for safety properties without building verification models. In our app...
Anh Vo, Sarvani S. Vakkalanka, Michael Delisi, Gan...