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» Verification of Timed Systems Using POSETs
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ENTCS
2006
112views more  ENTCS 2006»
13 years 6 months ago
Patterns for Timed Property Specifications
Patterns for property specification enable non-experts to write formal specifications that can be used for automatic model checking. The existing patterns identified in [6] allow ...
Volker Gruhn, Ralf Laue
ARTS
1997
Springer
13 years 10 months ago
The Verus Language: Representing Time Efficiently with BDDs
There have been significant advances on formal methods to verify complex systems recently. Nevertheless, these methods have not yet been accepted as a realistic alternative to the ...
Sérgio Vale Aguiar Campos, Edmund M. Clarke
AVBPA
2003
Springer
164views Biometrics» more  AVBPA 2003»
13 years 12 months ago
Personal Verification Using Palmprint and Hand Geometry Biometric
A new approach for the personal identification using hand images is presented. This paper attempts to improve the performance of palmprint-based verification system by integrating ...
Ajay Kumar, David C. M. Wong, Helen C. Shen, Anil ...
ICSE
2009
IEEE-ACM
13 years 4 months ago
VCC: Contract-based modular verification of concurrent C
Most system level software is written in C and executed concurrently. Because such software is often critical for system reliability, it is an ideal target for formal verification...
Markus Dahlweid, Michal Moskal, Thomas Santen, Ste...
EPK
2006
114views Management» more  EPK 2006»
13 years 8 months ago
Verifying Properties of (Timed) Event Driven Process Chains by Transformation to Hybrid Automata
Abstract: Event-driven Process Chains (EPCs) are a commonly used modelling technique for design and documentation of business processes. Although EPCs have an easy-to-understand no...
Stefan Denne