304 search results - page 8 / 61 » Verification of Timed Systems Using POSETs |
SIBGRAPI
2000
IEEE
13 years 11 months ago
2000
IEEE
This work has as main objective to present an off-line signature verification system. It is basically divided into three parts. The first one demonstrates a pre-processing process,...
HASE
1999
IEEE
13 years 11 months ago
1999
IEEE
Statechart Diagrams provide a graphical notation for describing dynamic aspects of system behaviour within the Unified Modeling Language (UML). In this paper we present a branchin...
SIES
2010
IEEE
13 years 4 months ago
2010
IEEE
Abstract--Many heterogeneous embedded systems, for example industrial automation and automotive applications, require hard-real time constraints to be exhaustively verified - which...
ISSS
2000
IEEE
13 years 11 months ago
2000
IEEE
The ever increasing complexity of embedded systems consisting of hardware and software components poses a challenge in verifying their correctness, New verification methods that o...
ENTCS
2006
13 years 6 months ago
2006
The approaches to automatic formal verification of UML models known up to now require a finite bound on the number of objects existing at each point in time. In [4] we have observ...