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» Verification of Timing Properties in Rapid System Prototypin...
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ARTS
1997
Springer
13 years 11 months ago
The Verus Language: Representing Time Efficiently with BDDs
There have been significant advances on formal methods to verify complex systems recently. Nevertheless, these methods have not yet been accepted as a realistic alternative to the ...
Sérgio Vale Aguiar Campos, Edmund M. Clarke
LPAR
2010
Springer
13 years 6 months ago
Synthesis of Trigger Properties
In automated synthesis, we transform a specification into a system that is guaranteed to satisfy the specification. In spite of the rich theory developed for temporal synthesis, l...
Orna Kupferman, Moshe Y. Vardi
TCAD
2002
137views more  TCAD 2002»
13 years 7 months ago
Generalized traveling-wave-based waveform approximation technique for the efficient signal integrity verification of multicouple
As very large scale integration (VLSI) circuit speed rapidly increases, the inductive effects of interconnect lines strongly impact the signal integrity of a circuit. Since these i...
Yungseon Eo, Seongkyun Shin, William R. Eisenstadt...
TRIDENTCOM
2008
IEEE
14 years 2 months ago
A flexible dual frequency testbed for RFID
This paper presents the setup of a testbed developed for the fast evaluation of RFID systems in two frequency domains. At the one hand the 13.56 MHz and at the other hand the 868 ...
Christoph Angerer, Martin Holzer 0002, Bastian Kne...
FMCAD
2000
Springer
13 years 11 months ago
Model Checking Synchronous Timing Diagrams
Abstract. Model checking is an automated approach to the formal verification of hardware and software. To allow model checking tools to be used by the hardware or software designer...
Nina Amla, E. Allen Emerson, Robert P. Kurshan, Ke...