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FORMATS
2007
Springer
13 years 11 months ago
Partial Order Reduction for Verification of Real-Time Components
Abstract. We describe a partial order reduction technique for a realtime component model. Components are described as timed automata with data ports, which can be composed in stati...
John Håkansson, Paul Pettersson
IJFCS
2006
110views more  IJFCS 2006»
13 years 7 months ago
Sat-based Model Checking for Region Automata
For successful software verification, model checkers must be capable of handling a large number of program variables. Traditional, BDD-based model checking is deficient in this re...
Fang Yu, Bow-Yaw Wang
ATVA
2008
Springer
144views Hardware» more  ATVA 2008»
13 years 9 months ago
Tests, Proofs and Refinements
1 : Logic in Specification and Verification (abstract) Natarajan Shankar (SRI) Session Chair : Sungdeok Cha 12 : 00 13 : 00 Lunch 13 : 00 15 : 00 2 : Boolean Modeling of Cell Biolo...
Sriram K. Rajamani
FM
2005
Springer
112views Formal Methods» more  FM 2005»
14 years 1 months ago
Dynamic Component Substitutability Analysis
This paper presents an automated and compositional procedure to solve the substitutability problem in the context of evolving software systems. Our solution contributes two techniq...
Natasha Sharygina, Sagar Chaki, Edmund M. Clarke, ...
CAV
2008
Springer
96views Hardware» more  CAV 2008»
13 years 9 months ago
Implied Set Closure and Its Application to Memory Consistency Verification
Hangal et. al. [3] have developed a procedure to check if an instance of the execution of a shared memory multiprocessor program, is consistent with the Total Store Order (TSO) mem...
Surender Baswana, Shashank K. Mehta, Vishal Powar