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FMCAD
2000
Springer
13 years 11 months ago
Model Checking Synchronous Timing Diagrams
Abstract. Model checking is an automated approach to the formal verification of hardware and software. To allow model checking tools to be used by the hardware or software designer...
Nina Amla, E. Allen Emerson, Robert P. Kurshan, Ke...
DAC
2006
ACM
14 years 8 months ago
Transistor abstraction for the functional verification of FPGAs
or Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdu...
Guy Dupenloup, Thierry Lemeunier, Roland Mayr
CORR
2010
Springer
208views Education» more  CORR 2010»
13 years 7 months ago
Bounded Model Checking of Multi-threaded Software using SMT solvers
The transition from single-core to multi-core processors has made multi-threaded software an important subject in computer aided verification. Here, we describe and evaluate an ex...
Lucas Cordeiro, Bernd Fischer 0002
DAC
2005
ACM
14 years 8 months ago
Minimising buffer requirements of synchronous dataflow graphs with model checking
Signal processing and multimedia applications are often implemented on resource constrained embedded systems. It is therefore important to find implementations that use as little ...
Marc Geilen, Twan Basten, Sander Stuijk
QEST
2006
IEEE
14 years 1 months ago
Compositional Performability Evaluation for STATEMATE
Abstract— This paper reports on our efforts to link an industrial state-of-the-art modelling tool to academic state-of-the-art analysis algorithms. In a nutshell, we enable timed...
Eckard Böde, Marc Herbstritt, Holger Hermanns...