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» Verification of timing Properties of VHDL
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FMCAD
2000
Springer
13 years 11 months ago
Model Checking Synchronous Timing Diagrams
Abstract. Model checking is an automated approach to the formal verification of hardware and software. To allow model checking tools to be used by the hardware or software designer...
Nina Amla, E. Allen Emerson, Robert P. Kurshan, Ke...
ECRTS
1999
IEEE
13 years 12 months ago
Timed automaton models for simple programmable logic controllers
We give timed automaton models for a class of Programmable Logic Controller (PLC) applications, that are programmed in a simple fragment of the language Instruction Lists as defin...
Angelika Mader, Hanno Wupper
LPAR
2010
Springer
13 years 5 months ago
Synthesis of Trigger Properties
In automated synthesis, we transform a specification into a system that is guaranteed to satisfy the specification. In spite of the rich theory developed for temporal synthesis, l...
Orna Kupferman, Moshe Y. Vardi
RTS
2006
176views more  RTS 2006»
13 years 7 months ago
Verifying distributed real-time properties of embedded systems via graph transformations and model checking
Component middleware provides dependable and efficient platforms that support key functional, and quality of service (QoS) needs of distributed real-time embedded (DRE) systems. C...
Gabor Madl, Sherif Abdelwahed, Douglas C. Schmidt
HYBRID
2007
Springer
13 years 11 months ago
Diagnosability Verification for Hybrid Automata
A notion of diagnosability for hybrid systems is defined, which generalizes the notion of observability. We verify bility properties on a timed automaton abstraction of the origina...
Maria Domenica Di Benedetto, Stefano Di Gennaro, A...