196 search results - page 15 / 40 » Verification of timing Properties of VHDL |
EURODAC
1994
IEEE
13 years 11 months ago
1994
IEEE
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
BIRTHDAY
2010
Springer
14 years 13 days ago
2010
Springer
Egon Börger Ambient Abstract State Machines with Applications 11:00 AM Manfred Broy Realizability of System Interface Specifications 11:30 AM Ofer Strichman Proving Equivalence be...
WCE
2007
13 years 8 months ago
2007
— The paper deals with the design and realization of a secure multicarrier modem on FPGA. The crypto-modem principle is adopted. An encryption block is integrated in the modem tr...
DFG
2004
Springer
13 years 11 months ago
2004
Springer
This paper presents the real-time model checker RAVEN and related theoretical background. RAVEN augments the efficiency of traditional symbolic model checking with possibilities to...
ECLIPSE
2006
ACM
13 years 11 months ago
2006
ACM
In this work we present an Eclipse plug-in for the VInTiMe (Verifier of INtegrated TImed ModEls)1 suite of tools that combines high-level expressive power, unassisted propertypres...