196 search results - page 17 / 40 » Verification of timing Properties of VHDL |
WIA
2000
Springer
13 years 11 months ago
2000
Springer
Abstract. We describe a general automata-theoretic approach for analyzing the verification problems (binary reachability, safety, etc.) of discrete timed automata augmented with va...
ISARCS
2010
13 years 9 months ago
2010
Methods of formal description and verification represent a viable way for achieving fundamentally bug-free software. However, in reality only a small subset of the existing operati...
FMOODS
2006
13 years 9 months ago
2006
Long-Running transactions consist of tasks which may be executed sequentially and in parallel, may contain sub-tasks, and may require to be completed before a deadline. These trans...
ENTCS
2002
13 years 7 months ago
2002
We report on the automatic verification of timed probabilistic properties of the IEEE 1394 root contention protocol combining two existing tools: the real-time modelchecker Kronos...
SIGSOFT
2007
ACM
14 years 8 months ago
2007
ACM
Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...